In recent years, there has been known a receiver apparatus which uses a digital modulation system such as a binary phase shift keying (BPSK) or the like. As a delayed detection circuit used in the receiver apparatus in which the digital modulation system as mentioned above is employed, for example, Patent Document 1 has been known. The delayed detection circuit shown in Patent Document 1, a low electric power consumption is achieved by substituting a shift register which is actuated at about 7.288 MHz with a sample hold circuit which is actuated at a symbol clock about 10 kHz.
In this case, in the receiver apparatus using the digital modulation system, there are included a physical layer circuit which carries out a process of a physical layer, and a media access control (MAC) circuit which carried out a MAC layer. The physical layer circuit detects a synchronous timing of the receiver signal and decodes the receiver signal in accordance with the detected synchronous timing so as to output a symbol string of 1, 0 to the MAC circuit. The MAC circuit makes the physical layer circuit cancel a capture of the synchronous timing if it detects a parity error from the symbol string which is output from the physical layer circuit or detects an end timing of the receiver signal.
However, the physical layer circuit starts a process for continuously capturing the synchronous timing if it cancels the capture of the synchronous timing. Accordingly, there is a possibility that the physical layer circuit captures the synchronous timing from a second half portion of the receiver signal in process of receiving if the cancellation of the capture of the synchronous timing is instructed from the MAC circuit in process of receiving one receiver signal. In this case, the physical layer circuit continuously carries out the decoding process in accordance with the synchronous timing unless the cancellation of the capture of the synchronous timing is instructed from the MAC circuit. As a result, the physical layer circuit cannot recognize the end of the receiver signal, and continuously carries out the decoding process in accordance with the captured synchronous timing during a no signal period until the next receiver signal comes, and it is impossible to accurately decode the next receiver signal. Further, Patent Document 1 does not devise any countermeasure while taking into consideration a problem that the decoding process is carried over during the no signal period.    Patent Document 1: Japanese Patent Application Laid-Open No. H5-183593